This is not about architecting a full SoC from scratch. You already have a competitive platform, now you want to add some kind of accelerator, maybe video, audio, ML, and need to explore architectural options for how accelerator and software should be partitioned, and to optimize PPA. Now we have AI to help us optimize you’d like … Read More
Artificial Intelligence
WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs
By Andy Nightingale, VP of Product Management and Marketing
As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More
Superhuman AI for Design Verification, Delivered at Scale
There is a new breed of EDA emerging. Until recently, EDA tools were focused on building better chips, faster and with superior quality of results. Part of that process is verifying and debugging the resultant design. Thanks to ubiquitous AI workloads and multi-chip architectures, the data to be verified and debugged is exploding,… Read More
AI Deployment Trends Outside Electronic Design
In a field as white-hot as AI it can be difficult to separate cheerleading from reality. I am as enthusiastic as others about the potential but not the “AI everywhere in everything” message that some emphasize. So it was interesting to find a survey which looks at the deployment reality outside our narrow domain of electronic and … Read More
AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation
In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence … Read More
How PCIe Multistream Architecture Enables AI Connectivity at 64 GT/s and 128 GT/s
As AI and HPC systems scale to thousands of CPUs, GPUs, and accelerators, interconnect performance increasingly determines end-to-end efficiency. Training and inference pipelines rely on low-latency coordination, high-bandwidth memory transfers, and rapid communication across heterogeneous devices. With model sizes… Read More
Jensen Huang Drops Donald Trump Truth Bomb on Joe Rogan Podcast
How’s that for a clickable title? It really should be called Jensen Huang’s origin story but who is going to click on that?
As podcaster myself I can say without a doubt that this was the best podcast I have listened to all year. During my 30+ EDA and IP career Nvidia was a customer on many different occasions. I do know how… Read More
An Assistant to Ease Your Transition to PSS
At times it has seemed like any development in EDA had to build a GenAI app that would catch the attention of Wall Street. Now I see more attention to GenAI being used for less glamorous but eminently more practical advances. This recent white paper from Siemens on how to help verification engineers get up to speed faster with PSS is … Read More
We Need to Turn Specs into Oracles for Agentic Verification
The natural language understanding now possible in LLMs has raised interest in using specs as a direct reference for test generation, to eliminate need for intermediate and fallible human translation. Sadly, specs today are not an infallible source of truth for multiple reasons. I am grateful to Shelly Henry (CEO of MooresLab)… Read More
Website Developers May Have Most to Fear From AI
Further on the theme of what jobs will AI displace or radically change, I have been thinking about Walmart’s recent announcement with OpenAI, to enable customers to buy products directly within ChatGPT. Seems far removed from any care-abouts in electronic design but bear with me. We’ve been hearing about sizeable layoffs at Amazon,… Read More


The Quantum Threat: Why Industrial Control Systems Must Be Ready and How PQShield Is Leading the Defense