After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More
Artificial Intelligence
Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000
Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions… Read More
Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond
As the computing industry seeks more flexible, scalable, and open hardware architectures, RISC-V has emerged as a compelling alternative to proprietary instruction set architectures. At the forefront of this revolution stands Andes Technology, offering a comprehensive lineup of RISC-V processor solutions that go far beyond… Read More
Voice as a Feature: A Silent Revolution in AI-Enabled SoCs
When Apple introduced Siri in 2011, it was the first serious attempt to make voice interaction a mainstream user interface. Embedded into the iPhone 4S, Siri brought voice into consumers’ lives not as a standalone product, but as a built-in feature—a hands-free way to interact with an existing device. Siri set the expectation… Read More
From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
In an era where artificial intelligence workloads are growing in scale, complexity, and diversity, chipmakers are facing increasing pressure to deliver solutions that are not only fast, but also flexible and programmable. Semidynamics recently announced Cervell™, a fully programmable Neural Processing Unit (NPU) designed… Read More
Alchip’s Technology and Global Talent Strategy Deliver Record Growth
Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building… Read More
The Journey of Interface Protocols: Adoption and Validation of Interface Protocols – Part 2 of 2
Part 2 examines the transformation of the interface protocols industry from a fragmented market of numerous specialized vendors to a more consolidated one dominated by a few major solutions providers as driven by the increasing complexity of modern protocols. It highlights the importance of rigorous validation of interface… Read More
CEO Interview with Thar Casey of AmberSemi
Thar Casey is a serial entrepreneur, focused on disruptive, game changing technology architecture. Today, he is the CEO of AmberSemi, a young California-based fabless semiconductor company advancing next-generation power management (conversion, control and protection) that revolutionizes electrical products and semiconductor… Read More
EDA AI agents will come in three waves and usher us into the next era of electronic design
Author: Niranjan Sitapure, AI Product Manager, Siemens EDA
We are at a pivotal point in Electronic Design Automation (EDA), as the semiconductors and PCB systems that underpin critical technologies, such as AI, 5G, autonomous systems, and edge computing, grow increasingly complex. The traditional EDA workflow, which includes… Read More
Webinar – Achieving Seamless 1.6 Tbps Interoperability with Samtec and Synopsys
It is well-known that AI is upending conventional wisdom for system design. Workload-specific processor configurations are growing at an exponential rate. Along with this is an exponential growth in data bandwidth needs, creating an urgency for 1.6T Ethernet. A recent SemiWiki webinar dove into these issues. Synopsys and … Read More
Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination